1. Field
Example embodiments relate to a maskless exposure apparatus and a method, and particularly to a maskless exposure apparatus and a method of using off-axis alignment to align a virtual mask and a substrate prior to exposure.
2. Description of the Related Art
Research and development is currently under way in the semiconductor industry to improve operation performance of various digital devices used in the industry, for example. As a result, a greater improvement in semiconductor device performance is achieved. For example, an exposure process to substantially reduce a line width of a circuit that is formed on the semiconductor is under development.
With the advancement of the information age, a flat panel display (FPD), such as a liquid crystal display (LCD), a plasma display panel (PDP), or electroluminescent display (ELD), exhibiting low power consumption has been developed. The size of the flat panel display has been increased based in part due to consumer demands, resulting in a development of overall process based equipment and methods. In particular, in a manufacturing process of the flat panel display, an exposure process to form a pattern on a display panel has been intensively developed.
That is, the exposure process is of relatively greater importance in the semiconductor and/or flat panel display field.
In the exposure process, light from a light source may be transmitted through a pattern of a photo mask, the light may be focused on a substrate, and exposure may be performed. In this mask type exposure process, however, high-resolution exposure may not be achieved due to the increase in manufacturing costs and management costs during exposure of a high-resolution micro circuit pattern.
For this reason, a maskless exposure process to achieve a line width of a super micro circuit is used.
In the maskless exposure process, light output from a light source is irradiated on a photosensitive film on a substrate according to a virtual mask pattern such that the photosensitive film is exposed in the form of a virtual mask pattern.
In the maskless exposure process, alignment between the virtual mask and the substrate (or wafer) is performed before exposure. At this time, when the alignment between the virtual mask and the substrate (or wafer) is performed using off-axis alignment, a baseline between an optical axis of pattern forming light and an optical axis of alignment light may drift.
Also, in a case in which a plurality of layers are exposed on a single substrate, alignment between each virtual mask and the substrate (or wafer) may be performed whenever each layer is disposed on the substrate. Also, the pattern forming light may be thermally deformed by external environmental changes, such as the increase of heat from a light source, due to the increase of processing time caused by the increase in number of layer disposition and exposure processes, with the result that the baseline between the optical axis of the pattern forming light and the optical axis of the alignment light may drift. A baseline drift amount resulting from the drift of the baseline causes an alignment error between the pattern forming light and the alignment light, thereby increasing an overlay error between layers.